Processing system, related integrated circuit, device and method
US12061530B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 16, 2022 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Oct 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.