Capacity-expanding memory control component
US12061793B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2022 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Aug 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2906
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoding engine within an integrated-circuit (IC) component iteratively executes error detection/correction operations with respect to a sequence of input data volumes to generate a corresponding sequence of error syndrome values, the input data volumes each including a first block of data and corresponding error correction code retrieved from one or more external memory components together with a respective one of a plurality of q-bit data patterns. Selector circuitry within the decoding engine selects one of the plurality of q-bit data patterns to be an output q-bit value according to error-count differentiation indicated by the error syndrome values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.