System with increasing protected storage area and erase protection
US12061803B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2021 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Oct 12, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7207
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus may include a processor. The apparatus may include a memory communicatively coupled to the processor. The apparatus may include a memory control circuit (MCC). The MCC may be configured to define a protected portion of the memory, wherein the protected portion of the memory is configured for read-only access by the processor, increase a size of the protected portion of the memory, and, after the increase in size of the protected portion of the memory, prevent decreases of the size of the protected portion of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.