Multi-dimensional network interface
US12061853B2 · kind B2 · utility
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4References
14Claims
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Key dates
| Filing date | Oct 8, 2021 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Jul 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein refer to a device having an integrated circuit with multiple tiers including a first tier and a second tier that are arranged vertically in a stacked configuration. The first tier may have first functional components, and the second tier may have second functional components. The device may have a three-dimensional (3D) connection within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.