Memory, memory controlling method and system
US12061913B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2023 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | May 27, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory, a method controlling method and a system are disclosed. The memory includes: an array of memory cells; an instruction decoder; a controller; and an I/O interface, including a chip select pin. The operational states of the memory include a deep power-down state, and in the deep power-down state, they are all disabled. In response to receiving a chip select signal, the memory enters a higher power state from the deep power-down state. The memory of the present disclosure provides the deep power-down state that disables the decoder, and the memory in the deep power-down state exits directly to a higher power state to achieve some functions without enabling all components, thereby reducing power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.