Systems and methods for clock frequency control during low display refresh rates in electronic devices
US12062313B2 · kind B2 · utility
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1References
20Claims
0Family size
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Key dates
| Filing date | Apr 6, 2023 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Apr 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/0435
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This disclosure is directed towards systems and methods of power saving in electronic displays based on changing clock signal frequencies supplied to the gate-in-panel (GIP) circuitry during extended blanking modes of the electronic display. The display driver circuitry of the display may reduce and/or halt clock signal frequencies sent to GIP circuitry in the display, to reduce power output during extended blanking modes of the electronic display.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.