Method for manufacturing semiconductor structure and semiconductor structure
US12062702B2 · kind B2 · utility
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4References
14Claims
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Key dates
| Filing date | Aug 23, 2021 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Nov 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for manufacturing a semiconductor structure, a substrate is provided; a stack layer is formed on the substrate, the stack layer including an interfacial layer, a high-k dielectric layer and a work function composite layer which are sequentially stacked; a transition layer is formed on the stack layer; and a metal gate layer is formed on the transition layer. The work function composite layer is prepared by a physical vapor deposition process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.