Output short-circuit protection method, power management chip and switched-mode power supply
US12062975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2022 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Apr 6, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An output short-circuit protection method, a power management chip and a switched-mode power supply are disclosed. When current accumulation has occurred in a power transistor, the number of consecutive current pulses during which the current accumulation occurred is counted. Upon the number of consecutive current pulses reaches a preset value, a regulation interval spanning switching periods is triggered, for at least some of the switching periods, the leading-edge blanking time is shortened or cancelled. In this way, an excessively large current flowing through the power transistor is prevented. Compared with existing fault response measures for power management chips, restart of the power supply and adjustment of the system timing are not needed, allowing easier implementation. Further, the automatic restart during chip start up due to false triggering as found in the existing measures for power management chips is circumvented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.