Multi-resolution cache
US12066942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2023 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Apr 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-resolution cache includes a first, second and third cache segments the first segment having a first resolution and the second and third segments having a second resolution, the second resolution less than the first resolution, the first and third cache segments communicatively coupled to an off-chip memory, the first and third cache segments configured to each receive a cache line of data having the first and second resolutions, a fourth and fifth cache segments having the second resolution, a first downscaler communicatively coupled to the first and fourth cache segments configured to reduce the resolution when a first resolution cached data is shifted from the first cache segment to the fourth cache segment, a first upscaler communicatively coupled to the all cache segments that have the second resolution, and is configured to increase the reduced resolution cached data to the first resolution and output it.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.