Multi-core processing and memory arrangement
US12066976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2023 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Aug 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2015/763
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention provides a generalized electronic computer architecture with multiple cores, memory distributed amongst the cores (a core-local memory). This arrangement provides predictable, low-latency memory response time, as well as a flexible, code-supplied flow of memory from one specific operation to another (using an operation graph). In one instantiation, the operation graph consists of a set of math operations, each accompanied by an ordered list of one or more input addresses. Input addresses may be specific addresses in memory, references to other math operations in the graph, or references to the next item in a particular data stream, where data streams are iterators through a continuous block of memory. The arrangement can also be packaged as a PCIe daughter card, which can be selectively plugged into a host server/PC constructed/organized according to traditional von Neumann architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.