Low latency SSD read architecture with multi-level error correction codes (ECC)
US12067254B2 · kind B2 · utility
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16References
20Claims
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Key dates
| Filing date | Mar 14, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Mar 14, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage unit is disclosed. The storage unit may include storage for a component codeword. The component codeword may be stored in a block in the storage. The block may also store a block codeword. An interface may receive a read request for a chunk of data from a host and may send the chunk of data to the host. A circuit may read the component codeword from the block in the storage. An error correcting code (ECC) decoder may determine the chunk of data based at least in part on the component codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.