CXL HDM decoding sequencing for reduced area and power consumption
US12067266B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Nov 8, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A total number V of virtual host-managed device memory (HDM) decoder configurations are generated for the same total number V of HDM memory regions attached to a non-host computing device. Each virtual HDM decoder configuration in the virtual HDM decoder configurations corresponds to a respective HDM memory region in the HDM memory regions. A proper subset of one or more virtual HDM decoder configurations is selected from among the virtual HDM decoder configurations to configure one or more physical HDM decoders of a total number P of the non-host computing device into one or more virtual HDM decoders. The one or more physical HDM decoders configured as one or more virtual HDM decoders are applied to translate a host physical address (HPA) received from a host computing device in a memory access transaction involving the host computing device and the non-host computing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.