Memory controller calculating optimal read level, memory system including the same, and operating method of memory controller
US12067287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Oct 9, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.