Partial rendering and tearing avoidance
US12067959B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2023 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Feb 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/04
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for receiving a synchronization signal from a display circuit configured to display a series of frames, each frame comprising a plurality of tiles of pixels, determining, based on the received synchronization signal, that the display circuit has consumed data corresponding to one or more tiles of a frame, identifying a predetermined number of tiles that are subsequent to the one or more tiles consumed by the display circuit based on the synchronization signal, determining that one or more tiles of the identified tiles require an update, selectively rendering the determined tiles, and transmitting the rendered tiles to the display circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.