Semiconductor apparatus and method for manufacturing the same
US12068014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2021 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Jun 6, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor apparatus includes a nonvolatile memory cell array including a plurality of first memory cells and a plurality of second memory cells including a first memory element 11 and a second memory element 12 including a resistance-variable nonvolatile memory element and a first selection transistor electrically connected to the first memory element 11 and the second memory element 12, in which a plurality of first memory elements 11 and a plurality of second memory elements 12 are arranged in a two-dimensional matrix in a first direction and a second direction different from the first direction and on the same interlayer insulating layer, the first memory element 11 is larger than the second memory element 12, and the first memory element 11 and the second memory element 12 are disposed adjacent to each other along the second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.