Power-up header circuitry for multi-bank memory
US12068025B2 · kind B2 · utility
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2References
19Claims
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Key dates
| Filing date | Jul 1, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Oct 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to a device having memory with banks of bitcells with each bank having a bitcell array. The device may have header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation. In some instances, only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.