Fin field-effect transistor (FinFET) based semiconductor memory array having memory cells using a reduced surface area
US12068027B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Feb 25, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fin field-effect transistor (FinFET) based semiconductor memory array having a plurality of memory cells, each memory cell including a write transistor having a write wordline gate over a first fin connected to a write wordline gate contact, a write bitline contact in connection with the first fin, and a storage node contact in connection with the first fin, and a read transistor having a storage node gate over a second fin, the storage node gate connected to a storage node gate contact, the storage node gate contact connected to the storage node contact, a read wordline contact in connection with the second fin, and a read bitline contact in connection with the second fin, wherein the write wordline gate and the storage node gate are arranged in series to each other along an extension axis that coincides with an longitudinal axis of the write wordline gate and a longitudinal axis of the storage node gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.