SRAM design for energy efficient sequential access
US12068054B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Sep 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM controller for performing sequential accesses using internal ports that operate concurrently on different rows. Each internal port includes a row address strobe (RAS) timer that generates clock signals controlling the timing of operations during a RAS phase in which word line decoding is performed once for a group of bit cells being accessed. The RAS phase can involve additional conditioning operations, such as precharging of local bits lines associated with the group of bit cells. The RAS phase is followed by an input/output (IO) phase in which individual bit cells are accessed in sequential address order using a column select signal generated by an IO timer. The RAS phase of a first internal port can be at least partially overlapped by the IO phase of a second internal port to hide the RAS latency of the first internal port. The IO timer can be shared among internal ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.