Method for fabricating semiconductor structure
US12068158B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2021 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Sep 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiment relates to a method for fabricating a semiconductor structure. The method includes: forming a first pattern on the first region and forming a second pattern on the second region, wherein the first pattern includes a plurality of first sub-patterns, a first gap is provided between adjacent two of the plurality of first sub-patterns, a width of the first gap is a first pitch, and wherein the second pattern includes a plurality of second sub-patterns, a second gap is provided between adjacent two of the plurality of second sub-patterns, a width of the second gap is a second pitch, and the second pitch is greater than the first pitch; forming a first mask layer on a sidewall of the first pattern, and forming a second mask layer on a sidewall of the second pattern; and removing the first pattern and the second pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.