Integrated circuit device and preparation method thereof
US12068202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2021 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Sep 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This application provides an integrated circuit device and a preparation method thereof, and relates to the field of semiconductor technologies. An isolation section for suppressing a leakage current path of two adjacent transistors may be formed by using a simple process. The integrated circuit device includes a substrate and a fin protruding from the substrate. The integrated circuit device further includes two adjacent transistors. The two adjacent transistors use two spaced segments on the fin as respective channels of the two adjacent transistors. A part that is of the fin and that is located between the two spaced segments is processed to obtain an isolation section. The isolation section is used to suppress current transfer between the two channels of the two adjacent transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.