Power semiconductor module with low inductance gate crossing
US12068290B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2020 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Apr 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power semiconductor module includes a main substrate and power semiconductor chips. Each power semiconductor chip is bonded to the main conductive layer with the first power electrode. A first group of the power semiconductor chips is connected in parallel via the second power electrodes and a second group of the power semiconductor chips is connected in parallel via the second power electrodes. The module also includes a first insulation layer and a first conductive layer overlying the first insulation layer as well as a second insulation layer and a second conductive layer overlying the second insulation layer. The first conductive layer provides a first gate conductor area and a first auxiliary emitter conductor area for the first group. The second conductive layer provides a second gate conductor area and a second auxiliary emitter conductor area for the second group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.