Semiconductor device including guard rings
US12068365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Jun 18, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a substrate; a guard ring disposed on the substrate and adjacent to an edge of the substrate; an integrated circuit structure surrounded by the guard ring and disposed on the substrate; and an insulating material structure disposed on a side surface of the guard ring, and wherein the guard ring includes a plurality of guard active structures on the substrate, a plurality of guard contact structures disposed on each of the plurality of guard active structures, and a guard interconnection structure disposed on a pair of guard contact structures adjacent to each other, among the plurality of guard contact structures, wherein each of the plurality of guard active structures includes a plurality of guard active fins spaced apart from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.