Transistor, ternary inverter including same, and transistor manufacturing method
US12068381B2 · kind B2 · utility
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3References
32Claims
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Key dates
| Filing date | Nov 19, 2020 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Jul 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transistor includes a substrate; a pair of constant current forming regions provided in the substrate; a pair of source/drain regions respectively provided on the pair of constant current forming regions in the substrate; and a gate structure provided between the pair of source/drain regions, wherein any one of the constant current forming regions immediately adjacent to any one of the pair of source/drain regions serving as a drain forms a constant current between the any one of the pair of source/drain region serving as the drain and the any one of the constant current forming regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.