Semiconductor device and manufacturing method thereof
US12068405B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Jul 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
Abstract
A method includes forming a semiconductor fin protruding above a substrate; forming a first 2D material layer across the semiconductor fin; depositing a gate material layer over the first 2D material layer; etching the gate material layer and the first 2D material layer to form a gate structure and a patterned first 2D material layer under the gate structure; laterally growing a second 2D material layer from the patterned first 2D material layer to beyond the gate structure; after laterally growing the second 2D material layer, forming gate spacers respectively on opposite sidewalls of the gate structure; and after forming the gate spacers, forming a third 2D material layer on the second 2D material layer until a combination of the third 2D material layer and the second 2D material layer comprises at least three or more monolayers of PtSe2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.