Dual-path high-speed interconnect PCB layout solution
US12068554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Nov 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3405
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A dual-path signal interconnect is provided. The interconnect can include a first signal trace, first and second solder pads positioned above and connected to the first signal trace, and a third solder pad. The second solder pad separates from the first solder pad. The third solder pad separates from the second solder pad and is connected to a second signal trace. The first and second solder pads are to allow a pin of a connector to be soldered to the first and second solder pads, such that, when the pin of the external connector is soldered, high-speed electrical signals from the first signal trace are routed to the connector. The second and third solder pads are to allow a conductor to be soldered to the second and third solder pads, such that, when the conductor is soldered, the high-speed electrical signals are routed to the second signal trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.