Noise mitigation circuitry for quantum computers and corresponding methods
US12068732B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 16, 2021 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Nov 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/01
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide methods, apparatuses, systems, or computer program products for providing a signal to an electrode of a quantum computer. In an example embodiment, the system comprises noise mitigation circuitry comprising a signal generator, a gain stage, and a filter stage. The signal generator may be comprised of a plurality of voltage sources. The controller causes the signal generator to generate a signal, and the signal is provided to the electrode through the noise mitigation circuitry to cause at least a portion of the system to perform a function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.