Digital loop filter of low latency and low operation and clock data recovery circuit including the same
US12068752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Nov 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0025
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.