Introduction and detection of erroneous stop condition in a single UART
US12068854B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Nov 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/201
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A universal asynchronous receiver/transmitter includes a transmission register to include information to be transmitted, a receive register to include information received, a frame error checking circuit to evaluate contents of the receive register for a frame error, and control logic. The control logic is to route the contents of the transmission register to the receive register. The control logic is to, during transmission of the contents of the transmission register through the reprogrammable pin to the receive register, modify a bit inversion register to yield modified contents to be provided to the receive register. The modified contents are to cause a frame error. The control logic is to determine whether the frame error checking circuit detected the frame error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.