Method and system to extend CMOS battery life
US12072745B2 · kind B2 · utility
0Cited by
7References
16Claims
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Key dates
| Filing date | Oct 15, 2021 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Nov 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system main board CMOS is powered by a CMOS battery, such as to keep a real time clock during a power off state, with the battery ground passed through a ground pad so that ground to the CMOS is incomplete until a coupling device, such as a screw, couples the main board to an information handling system housing. A bi-stable relay couples to the main board between the CMOS battery positive terminal and the CMOS to prevent application of power by the CMOS battery to the CMOS after closing of the ground until an embedded controller that is powered on the main board commands closing of the bi-stable relay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.