Resumable instruction generation
US12072789B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2022 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Feb 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating instruction sequences for testing a processor design model. The method includes receiving, by an instruction sequence generator (ISG), an initial test template. The initial test template includes an initial set of instruction constraints and a save resumable state command. The ISG generates a first set of executable test instructions based on the initial test template. The ISG initiates the save resumable state command. The ISG creates and saves a snapshot that includes information on a resume state of the ISG and the first set of executable test instructions at the time the save resumable state command is initiated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.