Anti-fuse array
US12073169B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2023 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Aug 9, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5252
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An anti-fuse array includes first through fourth adjacent anti-fuse bit columns, the anti-fuse bits of the first and second anti-fuse bit columns including portions of active areas of a first active area column, and the anti-fuse bits of the third and fourth anti-fuse bit columns including portions of active areas of a second active area column. Each row of a first set of conductive segment rows includes first and second conductive segments positioned between adjacent active areas of the first active area column and a third conductive segment positioned between adjacent active areas of the second active area column. Each row of a second set of conductive segments alternating with the first set of conductive segment rows includes a fourth conductive segment positioned between adjacent active areas of the first active area column and fifth and sixth conductive segments positioned between adjacent active areas of the second active area column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.