Full adder circuit and multi-bit full adder
US12073192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2023 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Oct 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/501
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application discloses a full adder circuit and a multi-bit full adder. In the full adder circuit, an in-memory computing field-effect transistor stores data and performs logic operation on the data in the transistor and the loaded data according to different input signals; and a low-area full adder circuit is realized with very few transistors through the characteristics and the reading and writing modes of the in-memory computing field-effect transistor. The full adder circuit has a simple structure, which is greatly reduces the area and complexity of the full adder circuit, and saves 19 transistors compared with the traditional CMOS full adder circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.