Real time sense and control using embedded instruction timing
US12073254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2021 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Aug 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for providing synchronous access to hardware resources includes a first network interface element to receive a network time signal from a data communication network and a memory to store sequence of one or more instructions selected from an instruction set of the first processing circuit. The sequence of one or more instructions include a first instruction that is configured to synchronize execution of a second instruction of the sequence of one or more instructions with the network time signal. The system further includes a first processing circuit to use the first instruction and a timing parameter associated with a second instruction to execute the second instruction in synchrony with the network time signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.