Barrier synchronization between host and accelerator over network
US12073262B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2021 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Jan 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A host system compiles a set of local programs which are provided over a network to a plurality of subsystems. By defining the synchronisation activity on the host, and then providing that information to the subsystems, the host can service a large number of subsystems. The defined synchronisation activity includes defining the synchronisation groups between which synchronisation barriers occur and the points during program execution at which data exchange with the host occurs. Defining synchronisation activity between the subsystems allows a large number of subsystems to be connecting whilst minimising the required exchanges with the host.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.