Gate driving circuit and display device including gate driving circuit
US12073794B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2022 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Nov 11, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/043
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.