Page buffer circuit and memory device including the same
US12073909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2022 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Feb 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.