Semiconductor memory devices
US12073910B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2023 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Feb 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.