Semiconductor device
US12074738B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2022 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Nov 18, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4917
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a comparison circuit configured to receive an input signal having n signal levels, where n is a natural number equal to or greater than three, and output n−1 first signals having two signal levels. The device includes a jitter compensation circuit configured to receive the n−1 first signals and compensate for at least one of a length of a period in which a signal level of at least one of the n−1 first signals transitions from a first signal level to a second signal level different from the first signal level, and a length of a period in which the signal level of the at least one of the n−1 first signals transitions from the second signal level to the first signal level, to output n−1 second signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.