Display apparatus
US12075661B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2023 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Jan 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1213
Abstract
A display apparatus includes a first TFT in a display area including a first semiconductor pattern including a polysilicon, a first gate electrode overlapping with the first semiconductor pattern under conditions that a first gate insulating layer is interposed, and first source and drain electrodes connected to the first semiconductor pattern, a second TFT in the display area including a second semiconductor pattern including a first oxide semiconductor, a second gate electrode overlapping with the second semiconductor pattern under conditions that second and third gate insulating layers are interposed, second source and drain electrodes connected to the second semiconductor pattern, and a third TFT in a non-display area including a third semiconductor pattern including a second oxide semiconductor, a third gate electrode overlapping with the third semiconductor pattern under conditions that the third gate insulating layer is interposed, and third source and drain electrodes connected to the third semiconductor pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.