Techniques for testing semiconductor devices
US12079097B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2020 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | May 10, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.