Memory system including memory device and memory controller, and operating method thereof
US12079491B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 5, 2023 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Feb 24, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory device including a memory cell array divided into a plurality of memory banks, and a memory controller that sends read requests or write requests to the memory device for the purpose of inputting data to or outputting data from the memory banks of the memory cell array, respectively, and sends the read requests so as to be separated from the write requests based on a read-write switching point. In a first turn, the memory controller sets a near switching point before the read-write switching point. The memory controller blocks scheduling at least one of first bank requests, between the near switching point and the read-write switching point. The memory controller schedules at least one of second bank requests, which cause state switching of the memory banks, so as to be issued between the near switching point and the read-write switching point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.