Nanofabrication and design techniques for 3D ICs and configurable ASICs

US12079557B2 · kind B2 · utility

Assignee

• The Board of Regents of the University of Texas System · US

Inventors

• Sidlgata V. Sreenivasan · Austin, US
• Paras Ajay · Austin, US
• Aseem Sayal · Austin, US
• Mark W. McDermott · Austin, US
• Jaydeep P. Kulkarni · Portland, US

Key dates

• Filing date: Sep 6, 2019
• Grant date: Sep 3, 2024
• Expiry date: Nov 3, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06544
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.