Control circuit, method for reading and writing and memory
US12080340B2 · kind B2 · utility
0Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 5, 2022 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Dec 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control circuit, a method for reading and writing and a memory are provided. The control circuit includes a pre-charge circuit, an amplification circuit and an equalization circuit. The pre-charge circuit is directly electrically connected to at least one of a bit line or a complementary bit line. The amplification circuit has a first node and a second node. The equalization circuit is connected between the first node and the bit line and between the second node and the complementary bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.