Memory device, integrated circuit device and method
US12080346B2 · kind B2 · utility
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13References
20Claims
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Key dates
| Filing date | May 17, 2022 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Oct 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a set of word lines, a set of bit lines, a source line having first and second source line contacts, a set of transistors serially coupled between the first and second source line contacts of the source line, and a set of data storage elements. The set of transistors has gates coupled to corresponding word lines in the set of word lines. Each data storage element in the set of data storage elements is coupled between a common terminal of a corresponding pair of adjacent transistors in the set of transistors, and a corresponding bit line in the set of bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.