System and method of power management in memory design
US12080372B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 9, 2022 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Dec 9, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a first virtual power line coupled to a power supply through a first group of transistor switches, and a second virtual power line configured to receive the power supply through a second group of transistor switches. The device also includes a delay circuit coupled between the gate terminals of the first group of transistor switches and the gate terminals in the second group of transistor switches. The device further includes a wakeup detector and a plurality of main input-output (MIO) controllers. The wakeup detector is configured to generate a trigger signal after receiving a signal from the output of the delay circuit. The plurality of MIO controllers is coupled to the power supply through a group of wakeup switches and through a group of function switches. The gate terminals in the group of wakeup switches are configured to receive the trigger signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.