Formation method of semiconductor structure
US12080589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2019 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Apr 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a formation method, comprising: forming a hard mask layer and a photo-lithographic pattern of a fin structure on a the semiconductor substrate; patterning the hard mask layer and the semiconductor substrate to gain the fin structure with a profile of steep sidewalls; forming a protective layer on the sidewall surface of the fin structure; etching the semiconductor substrate located below the fin structure to form isolation structure trenches; performing a modified treatment on the exposed surfaces of the isolation structure trenches to form a modified layer with a certain thickness; removing the protective layer and the modified layer simultaneously; filling a dielectric layer in the isolation structure trenches till to cover the fin structure and then planarizing the dielectric layer; performing a trench etching to the dielectric layer and forming the fin structure and an isolation structure with sloped sidewalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.