Semiconductor device including passivation patterns
US12080767B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2021 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Dec 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a first active pattern disposed on a substrate, a device isolation layer filling a trench that defines the first active pattern, a first channel pattern and a first source/drain pattern disposed on the first active pattern in which the first channel pattern includes semiconductor patterns stacked and spaced apart from each other, a gate electrode that extends and runs across the first channel pattern, a gate dielectric layer disposed between the first channel pattern and the gate electrode, and a first passivation pattern disposed between the device isolation layer and a first sidewall of the first active pattern. The first passivation pattern includes an upper part that protrudes upwardly from the device isolation layer, and a lower part buried in the device isolation layer. The gate dielectric layer covers the upper part of the first passivation pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.