Method of controlling wafer bow in a type III-V semiconductor device
US12080785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2022 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Jul 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes providing a type IV semiconductor substrate having a main surface, forming a type III-V semiconductor channel region over the type IV semiconductor substrate, the type III-V semiconductor channel region comprising a two-dimensional carrier gas, forming a type III-V semiconductor lattice transition region between the type IV semiconductor substrate and the type III-V semiconductor channel region, wherein forming the type III-V semiconductor lattice transition region incudes forming a first lattice transition layer over the type IV semiconductor substrate, the first lattice transition layer having a first metallic concentration, forming a third lattice transition layer over the first lattice transition layer, the third lattice transition layer having a third metallic concentration higher than the first metallic concentration, and forming a fourth lattice transition layer over the third lattice transition layer, the fourth lattice transition layer having a fourth metallic lower than the first metallic concentration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.