Electrostatic discharge protection network for chip
US12081018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2022 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Dec 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides an electrostatic discharge (ESD) protection network for a chip. The chip includes a first power supply pad, a second power supply pad, and a ground pad. The ESD protection network includes: a first ESD protection circuit, located between the first power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the first power supply pad; a second ESD protection circuit, located between the second power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the second power supply pad; and a third ESD protection circuit, configured to provide a discharge path for an electrostatic charge between the first power supply pad and the second power supply pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.