Pull up and pulldown stabiliser circuits and methods for gate drivers
US12081205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2023 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Mar 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Stabiliser circuits and methods are disclosed, for stabilizing a voltage at a gate driver terminal of a gate-driver for a driven transistor to a one of a high voltage and a low voltage, the stabilizer circuit comprising: a first transistor and a second transistor having respective first and second main terminals and connected in series between the gate voltage terminal and a first reference voltage terminal; and a low-pass filter connected between a control terminal of the first transistor and the gate driver terminal; wherein the first transistor is configured to have a threshold voltage which is less that a threshold voltage of the driven transistor; and the second transistor has a control terminal which is configured to be connected to a voltage which is an oppositive of the voltage at the gate driver terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.